Dr. Manoj Saxena

CONTACT INFORMATION
Department of Physics and Electronics
EMail: saxenamanoj77@gmail.com
Designation: Associate Professor
EDUCATION QUALIFICATIONS
B. Sc. Hons Electronics 1998 - Rajdhani College, University of Delhi
M. Sc. Electronics 2000 - Department of Electronic Science, University of Delhi
Ph. D Electronics 2006 - Department of Electronic Science, University of Delhi
CAREER PROFILE
ADMINISTRATIVE/ORGANIZATIONAL ASSIGNMENTS

Year 2013 – 2014

  • Convener – Website Committee
  • Convener – Career Counseling and Placement Cell
  • Member – College Archives Committee
  • Member – Alumni Committee of College
  • Convener- Committee for Sending Proposal to DU regarding MSME, Govt. of India.
  • Member – UGC XIITH Plan Grants Committee
  • Member – College NAAC Steering Committee
  • Member – College Research Council
  • Member – College Internal Quality Assuarnace Cell (IQAC)

Year 2012 – 2013

  • Convener – College Archives Committee
  • Convener - Prospectus Committee
  • Convener – Career Counseling and Placement Cell
  • Member – Website Committee
  • Member – Alumni Committee of College

Year 2011 – 2012

  • Convener – Career Counseling and Placement Cell
  • Member - Admission Committee
  • Member – Alumni Committee of College
  • Member – Departmental Technical and Purchase Committee

Year 2010 – 2011

  • Convener – Placement Cell
  • Member – Gandhi Study Circle, DDU College
  • Member – Rajiv Gandhi Study Circle, DDU College
  • Member – Alumni Committee of College
  • Member – Departmental Technical and Purchase Committee
  • Member – Lab. Development Committee for Electronics Labs in New Block

Year 2009 – 2010

  • Convener – Aryabhatta Science Forum
  • Member – Gandhi Study Circle, DDU College
  • Member – Rajiv Gandhi Study Circle, DDU College
  • Member - Prospectus Committee
  • Member – Canteen Committee
  • Member – Committee for purchase of office automation software for college
  • Member – Committee for renovation of furniture for staff room, principal office and seminar room of college

Year 2008 - 2009

  • Convener - Prospectus Committee
  • Member –Magazine Committee
  • Member – Canteen Committee
  • Member - Placement Cell
  • Member - Admission Committee
  • Member - Website Committee
  • Member – Aryabhatta Science Forum

Year 2007 - 2008

  • Convener - College Prospectus Committee
  • Co-Convener - Time Table Committee
  • Treasurer- DDUC Teaching Staff Association
  • Member - College Placement Cell
  • Member - Admission Committee
  • Member - Library Stock Verification Committee

Year 2006 - 2007

  • Convener - College Prospectus Committee
  • Member - College Placement Cell
  • Member - Admission Committee
  • Member - Library Stock Verification Committee
  • Member - Purchase Committee
  • Member - Departmental Lab. maintenance Committee

Year 2005 - 2006

  • Member - Student Activity Committee
  • Member - College Prospectus Committee
  • Member - College Website Committee
  • Member - Departmental Purchase Committee
  • Member - College Infrastructure Development Committee
  • Member - Proctorial Board
  • Member - Aryabhatta Science Forum
  • Member - Library Stock Verification Committee
  • Member - Admission Committee
  • Member - Purchase Committee
  • Treasurer- DDUC Teaching Staff Association

Year 2004 - 2005

  • Member - Technical Library Purchase Committee.
  • Member - Library Stock Verification Committee
  • Member - Departmental Technical Committee
  • Member - Departmental Time Table Committee
  • Member - Student Activity Committee
  • Member - Prospectus Committee
  • Member - Website Development Committee

Year 2003 - 2004

  • Member - Technical purchase Committee
  • Member - Discipline Committee
  • Member - Sports Committee 
SPECIALIZATIONS
  1. Electronics
  2. Semiconductor Device Modelling and Simulation
SUBJECTS TAUGHT
VLSI Circuit Design and Device Modeling - M. Sc. Electronics, Deptt of Electronic Science, Univ of Delhi IV Semester 2013, 2012, 2011
Advance Analog and Digital Electronics - M. Sc. Electronics, Deptt of Electronic Science, Univ of Delhi I Semester 2012, '11, '10, 2009
Advance Analog and Digital Electronics - M. Sc. Electronics, Deptt of Electronic Science, Univ of Delhi I Semester 2008, 2005, 2004
Introduction to Communication Systems - M. Sc. Informatics, IIC, Univ of Delhi I Semester 2005
Analog Electronics - B. Sc. (H) Electronics, DDU College, Univ of Delhi III Semester 2013, 2012, 2011
Signal and System - B. Sc. (H) Electronics, DDU College, Univ of Delhi II Semester 2013, 2012, 2011
Network Analysis - B. Sc. (H) Electronics, DDU College, Univ of Delhi I Semester 2010
Network Analysis and Linear Active circuits - B. Sc. (H) Electronics, DDU College, Univ of Delhi I Year '07 -'09, '02 - '04
Operational Amplifier and Analog Computation - B. Sc. (H) Electronics, DDU College, Univ of Delhi II Year 2005-2009
Numerical analysis and FORTRAN programming - B. Sc. (H) Electronics, DDU College, Univ of Delhi II Year 2007-2009
Engineering Drawing - B. Sc. (H) Electronics, DDU College, Univ of Delhi III Year 2003
Power Electronics - B. Sc. (H) Electronics, DDU College, Univ of Delhi III Year 2005, 2006
Communication System - B. Sc. (H) Electronics, DDU College, Univ of Delhi III Year 2002, 2003
Digital Electronics - B. Sc. (H) Computer, DDU College, Univ of Delhi I Semester 2004, 2005, 2006
Analog Electronics - B. Sc. (H) Computer, DDU College, Univ of Delhi II Semester 2003
Microprocessor - B. Sc. (H) Computer, DDU College, Univ of Delhi V Semester 2003, 2004
Semiconductor Devices - B. Tech Electronics Second Semester 2014
AREA OF RESEARCH
  1. Modeling and simulation of Epitaxial Channel and Drain Engineered, Dual/ Tripple Material Gate (DMG/ TMG), Silicon on Nothing (SON), Insulated Shallow Extension (ISE), Recessed Channel/ Grooved/ Concave Gate , Tunnel FET
RESEARCH GUIDANCE
Jointly Supervising Ms. Vandana Kumari, (Ph. D Candidate) since January, 2010 at Department of Electronic Science, University of Delhi South Campus, New Delhi. Jointly Supervising Mr. Ajay, (Ph. D Candidate) since July, 2013 at Department of Electronic Science, University of Delhi South Campus, New Delhi.
INVITED TALKS DELIVERED
  • “Applications of Quantum Mechanics in Nanoscale Electronics”, Second National Workshop On Quantum Mechanics: Theory and Application Organized By FiDAS, Deen Dayal Upadhyaya College, University of Delhi, Sponsored By CSIR, Govt of India Supported By IEEE EDS Delhi Chapter, New Delhi and The National Academy of Sciences, India, - Delhi Chapter held during October 22-23, 2010 and October 29-30, 2010.
  • “Applications of Quantum Mechanics in Nanoscale Electronics: Size Quantization Effect”, Physics Workshop organized by Kendriya Vidyalaya, R. K. Puram, Sector-2, New Delhi from December 24, 2010 to January 02, 2011
  • “Quantum Mechanics for Nanoelectronics” in Continuing Education Program (CEP) on “Nanoelectronics” from 17th – 21st January 2011 organized by Solid State Physics Laboratory, (laboratory under the Defence Research & Development Organization (DRDO), Govt. of India)
  • “Tunnel Field Effect Transistor – A Biomolecule Sensor”, Twenty Third Meeting of Indian Academy of Sciences, Bangalore held during 13th - 14th, July 2012.
  • Delievered Invited talk on “Information Handling”on May 24, 2013 during First Orientation Programme for Teachers of the Foundation Course – Information Technology organized by CPDHE-ILLL, University of Delhi during May 23-25, 2013
  • Delievered Invited talk on “Information Handling” on May 29, 2013 during Second Orientation Programme for Teachers of the Foundation Course – Information Technology organized by CPDHE-ILLL, University of Delhi during May 28-30, 2013
  • Delievered Invited talk on “Information Handling” on June 05, 2013 during Third Orientation Programme for Teachers of the Foundation Course – Information Technology organized by CPDHE-ILLL, University of Delhi during June 04-06 , 2013
  • Delievered Invited talk on “Information Handling” on June 13, 2013 during Fourth Orientation Programme for Teachers of the Foundation Course – Information Technology organized by CPDHE-ILLL, University of Delhi during June 12-14, 2013
  • Delievered Invited talk on “Information Handling” on June 29, 2013 during Orientation Programme (OR-74) organized by CPDHE, University of Delhi during June 20, 2013 – July 17, 2013
  • Delivered Invited Talk on " Information Technology" on July 17, 2013 during Master Class for First Year Students of different colleges of DU admitted under FYUP 2013 organized by CPDHE-ILLL, University of Delhi. The Master Classes for the Foundation Courses will bring 40 first year students from a few colleges for an Introductory session on 15 July (getting to know the university), to be followed by two days of intensive classes on 16 and 17 July for seven Foundation Courses.
  • Delivered Invited talk on “Information Handling” on July 27, 2013 during Fifth Orientation Programme for Teachers of the Foundation Course – Information Technology organized by CPDHE-ILLL, University of Delhi during July 26, 2013 - July 29, 2013
  • Delivered Invited talk on “Information Handling” on January 19, 2014 during Sixth Orientation Programme for Teachers of the Foundation Course – Information Technology organized by CPDHE-ILLL, University of Delhi during January 18 , 2014 - January 19, 2014
BOOK/BOOK CHAPTER/MONOGRAPH PUBLISHED
  • Member - Editorial Board - Proceedings of 16th Asia Pacific Microwave Conference 2004, Department of Electronic Science, University of Delhi, Allied Publishers Pvt. Ltd. 2004, ISBN 81-7764-722-9.
  • Book Chapter - MOSFET Modeling, R. S. Gupta, Mridula Gupta and Manoj Saxena, Encyclopedia of RF and Microwave Engineering, John-Wiley & Sons, Inc. New Jersey, USA, March 2005, pp. 3278-3317, ISBN: 0-471-27053-9.
  • Proceeding Editor - National Conference on Mathematical Techniques: Emerging Paradigms for Electronics and IT Industries (MATEIT-2006) from 22nd March – 25th March 2006, Deen Dayal Upadhyaya College, University of Delhi, Shivaji Marg, New Delhi, India, ISBN: 81-8424-026-0
  • E-Proceeding Editor - National Conference on Mathematical Techniques: Emerging Paradigms for Electronics and IT Industries (MATEIT-2008) from 26th September – 28th September 2008, Deen Dayal Upadhyaya College, University of Delhi, Shivaji Marg, New Delhi, India
  • Editor – Proceeding of the International Symposium on Microwave and Optical Technology (ISMOT)-2009, December 16-19, 2009.
  • Proceeding Editor - Third National Conference on Mathematical Techniques: Emerging Paradigms for Electronics and IT Industries (MATEIT-2010) held during January 30-31, 2010, Deen Dayal Upadhyaya College, University of Delhi, Shivaji Marg, New Delhi, India, sponsored By University Grants Commission (UGC), Govt. of India
  • “Information Technology”, D. V. Singh, Shailender Kumar, Neeraj Tyagi, Pankaj Tyagi, Sanjeev Singh, Manoj Saxena and Ranjan Kumar, Universities Press, ISBN 9788173719004 (2013)
PAPERS IN INTERNATIONAL JOURNALS
  1. Physics Based Analytical Modeling of Potential and Electrical Field Distribution in Dual Material Gate (DMG)-MOSFET for Improved Hot Electron Effect and Carrier Transport Efficiency, Manoj Saxena, Subhasis Haldar, Mridula Gupta, and R. S. Gupta, IEEE Transaction on Electron Devices, Vol. 49, No. 11, pp. 1928-1938, November 2002
  2. Physics Based Modeling and Simulation of Dual Material Gate Stack (DUMGAS) MOSFET, Manoj Saxena, Subhasis Haldar, Mridula Gupta and R. S. Gupta, IEE Electronics Letter, 9th January, Vol. 39, No.1, pp-155-157, January 2003.
  3. Modeling and simulation of asymmetric gate stack (ASYMGAS)-MOSFET, Manoj Saxena, Subhasis Haldar, Mridula Gupta and R. S. Gupta, Solid State Electronics, Vol. 47, pp. 2131-2134, 2003.
  4. Design considerations for novel device architecture: Hetro -Material Double-Gate (HEM-DG) MOSFET with sub –100 nm gate length Manoj Saxena, Subhasis Haldar, Mridula Gupta and R.S. Gupta, Solid State Electronics Vol. 48, pp. 1169-1174, 2004.
  5. Optimization of Gate stack MOSFETs with Quantization effects, Tina Mangla, Amit Sehgal, Manoj Saxena, Subhasis Haldar, Mridula Gupta and R. S. Gupta, Journal of Semiconductor Science and Technology (JSTS), Vol.4, No.3, pp. 228-239, September 2004.
  6. Two-Dimensional Analytical Modeling and Simulation of Retrograde doped HMG MOSFET, Kirti Goel, Manoj Saxena, Mridula Gupta and R.S. Gupta, International Journal of High Speed Electronics and Systems, Vol.14, No.3, pp.676-683, September 2004.
  7. Two-Dimensional Analytical Threshold Voltage Model for Dual Material Gate (DMG) Epi-MOSFET, Kirti Goel, Manoj Saxena, Mridula Gupta and R.S. Gupta, IEEE Transactions on Electron Devices, Vol.52, No.1, pp.23-29, January 2005.
  8. Physics-based algorithm implementation for characterization of gate dielectric engineered MOSFETs including Quantization effects, Tina Mangla, Amit Sehgal, Manoj Saxena, Subhasis Haldar, Mridula Gupta and R. S. Gupta, Journal of Semiconductor Science and Technology (JSTS), Vol.5, No.3, pp.69-77, September 2005.
  9. Modeling and Simulation of Stacked Gate Oxide (STGO) Architecture in Silicon-On-Nothing (SON) MOSFET Poonam Kasturi, Manoj Saxena and R.S. Gupta, Solid State Electronics, Vol. 49, No. 10, pp. 1639-1648,October 2005.
  10. Modeling and Simulation of a Nanoscale Three Region Tri MAterial Gate Stack (TRIMGAS) MOSFET for Improved Carrier Transport Efficiency and Reduced Hot Electron Effects, IEEE Transactions on Electron Devices, Kirti Goel, Manoj Saxena, Mridula Gupta and R. S. Gupta, Vol. 53, No. 7, pp. 1623-1633, July 2006.
  11. Two-Dimensional Analysis and Simulation for Gate Stack Silicon-On-Nothing MOSFET (GAS-SON MOSFET), Poonam Kasturi, Manoj Saxena, R.S. Gupta, International Journal of Microwave and Optical Technology Letter (IJMOT), Vol. 1, No. 2, pp. 417-421, August 2006.
  12. Performance Investigation of 50nm Insulated Shallow Extension Gate Stack (ISEGaS) MOSFET for Mixed Mode Applications, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, IEEE Transactions on Electron Devices, Vol. 54, No.2, pp. 365-368, February 2007.
  13. Unified model for physics based modeling of a new device architecture:Triple Material Gate Oxide Stack Epitaxial Channel Profile (TRIMGASEpi) MOSFET, Kirti Goel, Manoj Saxena, Mridula Gupta and R. S. Gupta, Semiconductor Science and Technology, vol. 22, pp. 435-446, 2007.
  14. Hot carrier reliability and analog performance investigation of DMG-ISEGaS MOSFET Ravneet Kaur, Rishu Chaujar, Manoj Saxena, and R. S. Gupta, IEEE Transactions on Electron Devices, Vol. 54, No. 9, pp. 2556-2561, September 2007.
  15. Unified Subthreshold Model for Channel Engineered Sub-100nm Advanced MOSFET Structures Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, IEEE Transactions on Electron Devices Vol. 54, No. 9, pp. 2475-2486, September 2007.
  16. Two-Dimensional Analytical Model to Characterize Novel MOSFET Architecture: Insulated Shallow Extension (ISE) MOSFET, Ravneet Kaur, Rishu Chaujar, Manoj Saxena, and R. S. Gupta Semiconductor Science Technology, Vol.22, pp. 952-962, 2007.
  17. Lateral channel engineered- hetero material insulated shallow extension gate stack (HMISEGAS) MOSFET structure: high performance RF solution for MOS technology Ravneet Kaur, Rishu Chaujar, Manoj Saxena, and R. S. Gupta Semiconductor Science Technology, Vol. 22, No.10, pp. 1097-1103, 2007.
  18. Dual Material Double Layer Gate Stack SON MOSFET: A Novel Architecture for enhanced analog performance – Part I Impact of Gate Metal Workfunction Engineering, Poonam Kasturi, Manoj Saxena, Mridula Gupta and R.S. Gupta, IEEE Transactions on Electron Devices, Vol. 55, No. 1, pp. 372-381, January 2008.
  19. Dual Material Double Layer Gate Stack SON MOSFET: A Novel Architecture for enhanced analog performance – Part II Impact of Gate Dielectric Material Engineering, Poonam Kasturi, Manoj Saxena, Mridula Gupta and R.S. Gupta, IEEE Transactions on Electron Devices, Vol. 55, No. 1, pp. 382-387, January 2008.
  20. Laterally amalgamated DUal Material GAte Concave (L-DUMGAC) MOSFET For ULSI, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Microelectronic Engineering, Vol. 85, No. 3, pp. 566-576, March 2008.
  21. Two-dimensional analytical sub-threshold model of multi-layered gate dielectric recessed channel (MLaG-RC) nanoscale MOSFET, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Semiconductor Science Technology Vol.23, 045006 (10pp) 2008.
  22. Intermodulation Distortion and Linearity Performance Assessment of 50-nm gate length L-DUMGAC MOSFET for RFIC Design, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, Superlattices and Microstructures, Vol.44, pp. 143-152, 2008.
  23. On-state and RF performance investigation of sub-50nm L-DUMGAC MOSFET design for high-speed logic and switching applications, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Semiconductor Science Technology, 23 095009 (8pp), 2008.
  24. TCAD Assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and its Multi-Layered Gate Architecture: Part-I: Hot Carrier Reliability Evaluation, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, IEEE Transactions on Electron Devices, Vol. 55, No. 10, pp. 2602-2613, October 2008.
  25. A TCAD Study of Sub-100nm Advance Gate Electrode Workfunction Engineered SON MOSFET, R S Gupta, Manoj Saxena and Poonam Kasturi, International Journal of Microwave and Optical Technology Letter (IJMOT), Vol. 3, No. 3, pp. 190-195, July 2008.
  26. Investigation of Multi-Layered-Gate Electrode Workfunction Engineered Recessed Channel (MLGEWE-RC) Sub-50nm MOSFET: A Novel Design, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, International Journal of Numerical Modeling: Electronic Networks, Devices and Fields, Wiley, Vol. 22, No. 3, pp. 259-278, March/ April 2009.
  27. Two-dimensional threshold voltage model and design considerations for gate electrode workfunction engineered recessed channel (GEWE-RC) nanoscale MOSFET: part I, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, Semiconductor Science Technology, Vol. 24, No 6, 065005 (10pp), (June 2009)
  28. Two Dimensional Simulation and Analytical Modeling of a Novel ISE MOSFET with Gate Stack Configuration, Ravneet Kaur, Rishu Chaujar, Manoj Saxena, Mridula Gupta and R. S. Gupta, Microelectronic Engineering, Volume 86, Issue 10, Pages 2005-2014, October 2009
  29. TCAD assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and its multi-layered gate architecture, Part II: Analog and large signal performance evaluation, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, Superlattices and Microstructures, Volume 46, Issue 4, Pages 645-655, October 2009
  30. Hot-Carrier Reliability Monitoring of DMG ISE SON MOSFET for improved Performance, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R.S. Gupta, Microwave and Optical Technology Letter, pp. 652-657, Vol. 52, No. 3, March 2010.
  31. Design Considerations and Impact of Technological papramteric variations on RF/Microwave performance of GEWE-RC MOSFET, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, Microwave and Optical Technology Letter, pp. 770-775, Vol. 52, No. 3, March 2010.
  32. Effect of Temperature and Gate Stack on the Linearity and Analog Performance of Double Gate Tunnel FET, Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, Trends in Network and Communications, Proceedings of International Conferences, NeCOM, WeST, WiMoN 2011, Chennai, India, July 15-17, 2011, Edited by David C. Wyld, Michal Wozniak, Nabendu Chaki, Natarajan Meghanathan and Dhinaharan Nagamalai, Communications in Computer and Information Science, Volume 197, Part 2, 466-475, 2011
  33. Channel Material Engineered Nanoscale Cylindrical Surrounding Gate MOSFET with Interface Fixed Charges, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, Trends in Network and Communications, Proceedings of International Conferences, NeCOM, WeST, WiMoN 2011, Chennai, India, July 15-17, 2011, Edited by David C. Wyld, Michal Wozniak, Nabendu Chaki, Natarajan Meghanathan and Dhinaharan Nagamalai, Communications in Computer and Information Science, Volume 197, Part 2, 476-485, 2011
  34. Impact of Interface Fixed Charges on the Performance of the Channel Material Engineered Cylindrical Nanowire MOSFET, Rajni Gautam, Manoj Saxena, R. S. Gupta, and Mridula Gupta, International journal of VLSI design & Communication Systems ( VLSICS ), Vol. 2, No. 3, pp. 225-241, September 2011
  35. Linearity and Analog Performance analysis of Double Gate Tunnel FET: Effect Temperature and Gate Stack, Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, International journal of VLSI design & Communication Systems ( VLSICS ), Vol. 2, No. 3, pp. 185-200, September 2011
  36. Fabrication and Time Degradation study of Mercuric Iodide (Red) Single Crystal X-Ray Detector, Kulvinder Singh, Manoj Saxena, J. Nano- Electron. Phys.3 (2011) No. 1, pp. 802-807, 2011
  37. High Sensitivity Photodetector Using Si/Ge/GaAs Metal Semiconductor Field Effect Transistor (MESFET), Rajni Gautam, Manoj Saxena, R. S. Gupta, and Mridula Gupta, International Conference on Light :Optics 2011: Phenomenon, Materials, Devices and Charecterization, Kerala, (India), 23–25 May 2011, AIP Conference Proceedings Volume 1391, pp. 232-234.
  38. Dielectric Modulated Tunnel Field Effect Transistor - A Bio molecule Sensor, Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, IEEE Electron Device Letter, Vol. 33, No. 2, pp.266-268 , February 2012
  39. Temperature Dependent Drain Current Model for Gate Stack Insulated Shallow Extension Silicon On Nothing (ISESON) MOSFET For Wide Operating Temperature Range, Vandana Kumari, Manoj Saxena, R. S. Gupta, and Mridula Gupta, Microelectronics Reliability, Vol. 52, pp. 974-983, June 2012
  40. Effect of localized charges on Nanoscale Cylindrical Surrounding Gate MOSFET: Analog performance and Linearity Analysis, Rajni Gautam, Manoj Saxena, R. S. Gupta, and Mridula Gupta, Microelectronics Reliability, Vol. 52, pp. 989-994, June 2012
  41. Two Dimensional Analytical Subthreshold Model of Nanoscale Cylindrical Surrounding Gate MOSFET Including Impact of Localised Charges, Rajni Gautam, Manoj Saxena, Mridula Gupta and R. S. Gupta, Journal of Computational and Theoretical Nanoscience (CTN), Vol. 9, No.4, pp. 602-610, April 2012
  42. Simulation Study of Insulated Shallow Extension Silicon On Nothing (ISESON) MOSFET for High Temperature Applications, Vandana Kumai, Manoj Saxena, R. S. Gupta and Mridula Gupta, Microelectronics Reliability, Volume 52, Issue 8, Pages 1610-1612,August 2012.
  43. Immunity Against Temperature Variability and Bias Point Invariability in Double Gate Tunnel Field Effect Transistor, Rakhi Narang, Manoj Saxena, R. S. Gupta, and Mridula Gupta, Microelectronics Reliability, Volume 52, Issue 8, Pages 1617-1620, August 2012.
  44. Two Dimensional Analytical Drain Current Model for Double Gate MOSFET Incorporating Dielectric Pocket (DP-DG), Vandana Kumari, Manoj Saxena, R. S. Gupta, and Mridula Gupta, IEEE Transactions on Electron Devices, Vol. 59, No. 10, pp. 2567-2564, October 2012
  45. A Dielectric Modulated Tunnel FET based Biosensor for Label Free Detection: Analytical Modeling Study and Sensitivity Analysis, Rakhi Narang, K. V. Sasidhar Reddy, Manoj Saxena, R. S. Gupta, and Mridula Gupta, IEEE Transactions on Electron Devices, Vol. 59, No. 10, pp. 2809-2817, October 2012
  46. Stability Study on Ceramic Mercuric Iodide (Red) X-Ray Sensor, Kulvinder Singh and Manoj Saxena, Proc. SPIE 8549, 16th International Workshop on Physics of Semiconductor Devices, 854910 (October 15, 2012); doi: 10.1117/12.924240
  47. An Analytical Modeling Approach for a Gate All Around (GAA) Tunnel Field Effect Transistor, Rakhi Narang, Manoj Saxena, R. S. Gupta, and Mridula Gupta, Proc. SPIE 8549, 16th International Workshop on Physics of Semiconductor Devices, 854906 (October 15, 2012); doi: 10.1117/12.925534
  48. Digital Circuit Analysis of Insulated Shallow Extension Silicon On Void (ISESOV) FET for Low Voltage Applications, Vandana Kumari, Manoj Saxena, R. S. Gupta, and Mridula Gupta, Proc. SPIE 8549, 16th International Workshop on Physics of Semiconductor Devices, 854905 (October 15, 2012); doi: 10.1117/12.925533
  49. Numerical Model of Gate All Around MOSFET With Vacuum Gate Dielectric For Biomolecule Detection, Rajni Gautam, Manoj Saxena, R. S. Gupta, and Mridula Gupta, IEEE Electron Device Letter, Vol. 33, No. 12, pp. 1756-1758, December 2012
  50. Assessment of Ambipolar Behavior of a Tunnel FET and Influence of Structural Modifications, Rakhi Narang, Manoj Saxena, R. S. Gupta, and Mridula Gupta, Journal of Semiconductor Science and Technology (JSTS), Vol.12, No.4, pp. 482-491, December, 2012
  51. Numerical Analysis of Localised Charges Impact on the Static and Dynamic Performance of Nanoscale Cylindrical Surrounding Gate MOSFET Based CMOS Inverter, Rajni Gautam, Manoj Saxena, R. S. Gupta, and Mridula Gupta, Microelectronics Reliability, pp. 236-244, 2013
  52. Analog and Digital Performance Assessment of Empty Space in Double Gate (ESDG) MOSFET: A Novel Device Architecture, Vandana Kumari, Manoj Saxena, R. S. Gupta, and Mridula Gupta, Journal of Computational and Theoretical Nanoscience, Volume 10, Number 2, pp. 389-398, February 2013
  53. Hot Carrier Reliability of Gate All Around MOSFET for RF/Microwave Applications, Rajni Gautam, Manoj Saxena, R. S. Gupta, and Mridula Gupta, IEEE Transactions on Device and Materials Reliability, Vol. 13, No. 1, pp. 245-250, March 2013
  54. Investigation of Empty Space in Nanoscale Double Gate (ESDG) MOSFET for High Speed Digital Circuit Applications, Vandana Kumari, Manoj Saxena, R. S. Gupta, and Mridula Gupta, Journal of Semiconductor Science and Technology (JSTS), Vol. 13, No. 2, pp. 127-138, April 2013
  55. Device and Circuit Level Performance Comparison of Tunnel FET Architectures and Impact of Heterogeneous Gate Dielectric”, Rakhi Narang, Manoj Saxena, R. S. Gupta, and Mridula Gupta, Journal of Semiconductor Science and Technology (JSTS), Vol. 13, No.3, pp. 224-236, June 2013
  56. Analytical Model for Double-Gate Tunneling Field-Effect Transistor (DG-TFET) using carrier concentration approach, Rakhi Narang, Manoj Saxena, R. S. Gupta, and Mridula Gupta, Journal of Computational and Theoretical Nanoscience (JCTN), Volume 10, Number 5 (May 2013) pp.1202-1208 (2013)
  57. Circuit Level Implementation for Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET: A Novel Device Architecture, Vandana Kumari, Manoj Saxena, R. S. Gupta, and Mridula Gupta, IETE Journal of Research, Volume 59, Issue 4, pp. 404-409, 2013
  58. Gate All Around MOSFET With Vacuum Gate Dielectric for Improved Hot Carrier Reliability and RF Performance, Rajni Gautam, Manoj Saxena, R. S. Gupta, and Mridula Gupta, IEEE Transactions on Electron Devices, Vol. 60, No. 6, pp. 1820-1827, June 2013
  59. Comparative Study of Silicon On Nothing and III-V On Nothing Architecture for High Speed and Low Power Analog and RF/Digital Applications, Vandana Kumari, Manoj Saxena, R. S. Gupta, and Mridula Gupta, IEEE Transactions on Nanotechnology, Vol. 12, No. 6, pp.978-984, November 2013
  60. Impact of Temperature variations on the Device and Circuit Performance of Tunnel FET: A Simulation Study, IEEE Transactions on Nanotechnology, Rakhi Narang, Manoj Saxena, R. S. Gupta, and Mridula Gupta, IEEE Transactions on Nanotechnology, Vol. 12, No. 6, pp.951-957, November 2013
  61. Gate All Around MOSFET with Catalytic Metal gate for Gas Sensing Applications, Rajni Gautam, Manoj Saxena, R. S. Gupta, and Mridula Gupta, IEEE Transactions on Nanotechnology, Vol. 12, No. 6, pp.939-944, November 2013
  62. Drain current model for a gate all around (GAA) p–n–p–n tunnel FET, Rakhi Narang , Manoj Saxena , R.S. Gupta, Mridula Gupta, Microelectronics Journal, Volume 44, Issue 6, pp. 479–488, June 2013.
  63. Analytical Model of Double Gate MOSFET for High Sensitivity Low Power Photosensor, Rajni Gautam, Manoj Saxena, R. S. Gupta, and Mridula Gupta, Journal of Semiconductor Science and Technology (JSTS), Vol. 13, No.5,pp. 500-510, October 2013
  64. Performance Investigation of Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET for Low Voltage Digital Applications, Vandana Kumari, Manoj Saxena, R. S. Gupta, and Mridula Gupta, Journal of Semiconductor Science and Technology (JSTS), Vol. 13, No.6,pp. 622-634, December 2013
  65. Temperature Dependent Subthreshold Model of Long Channel GAA MOSFET Including Localized Charges to Study Variations in its Temperature Sensitivity, Rajni Gautam, Manoj Saxena, R. S. Gupta, and Mridula Gupta, Microelectronics Reliability, 4 ( 1 ) pp. 37 – 43, 2014
  66. Analytical Modeling of Dielectric Pocket Double Gate (DP-DG) MOSFET Incorporating Hot Carrier Induced Interface Charges, Vandana Kumari, Manoj Saxena, R. S. Gupta and Mridula Gupta, Accepted for publication in IEEE Transactions on Device and Material Reliability
PAPERS IN INTERNATIONAL CONFERENCE PROCEEDINGS
  1. Closed form Analytical Threshold Voltage Model of Dual Material Double-Gate (DUM-DG) MOSFET, Manoj Saxena, Subhasis Haldar, Mridula Gupta, and R. S. Gupta, 15th Asia Pacific Microwave Conference (APMC-2003), November 4-7, 2003, Seoul, Korea, pp. 1434-1437.
  2. Two-Dimensional analytical modeling and simulation of retrograde doped HMG-MOSFET, R. S. Gupta, Kirti Goel, Manoj Saxena and Mridula Gupta, IEEE Lester Eastman Conference, August 4-6, 2004,Troy, New York, USA, pp. 84-85.
  3. Physics Based Modeling and Simulation of Epitaxial Channel Hetero Material Gate Stack (EPI-HEMGAS MOSFET), Kirti Goel, Manoj Saxena, Mridula Gupta and R. S. Gupta, 16th Asia Pacific microwave Conference, APMC, December 15th –18th, 2004, New Delhi, India, pp. 9-10.
  4. Analytical Analysis and Simulation of High-K Dielectric in Gate Stack Silicon on Nothing (GAS-SON) MOSFET for Sub-100 nm Gate Length, Poonam Kasturi, Manoj Saxena, R.S. Gupta, 16th Asia Pacific Microwave Conference, APMC, December 15th –18th, 2004, New Delhi, India, pp. 65-67
  5. HEMGAS: A Novel Gate Workfunction Engineered Stacked Gate Oxide Concept for Sub-50 nm DG-MOSFET, Manoj Saxena, Subhasis Haldar, Mridula Gupta, and R. S. Gupta, 2nd International conference on Computer and Devices for communications, CODEC-2004, January 1-3, 2004 in Calcutta, India, pp. 155
  6. Two-Dimensional Analysis and Simulation for Gate Stack Silicon-On-Nothing MOSFET (GAS-SON MOSFET), Poonam Kasturi, Manoj Saxena, R.S. Gupta, 10th International Symposium on Microwave and Optical Technology, ISMOT 2005, Fukuoka, Japan, August 22–25, 2005, pp. 406-409
  7. Dual-Material Gate Asymmetric Oxide (DMGASYMOX) Stack MOSFET: A Novel Device Architecture for Improved Carrier Transport Efficiency and Reduced Hot Electron Effects, Kirti Goel, Manoj Saxena, Mridula Gupta, R. S. Gupta International Union of Radio Science (URSI), New Delhi, India, October 23-29, 2005.
  8. Non-Uniformly Doped Gate Electrode Workfunction Engineered MOSFET: Novel Design Architecture for Controlling Short Channel Effect and Improving Gate Transport Efficiency, R. S. Gupta, Kirti Goel, Manoj Saxena and Mridula Gupta, Thirteenth International Workshop on The Physics of Semiconductor Devices (IWPSD), New Delhi, India, December 13-17, 2005, pp. 995-1002.
  9. Investigating the role of Stacked Gate Oxide and Hetro-Material Gate on Electrical Characteristics of Insulated Shallow Extension (ISE) MOSFET Ravneet Kaur, Manoj Saxena and R. S. Gupta, Thirteenth International Workshop on The Physics of Semiconductor Devices (IWPSD), New Delhi, India, December 13-17, 2005 pp. 1163-1166.
  10. Physics based modeling and simulation of Hetero-Material Asymmetric Gate Stack Epi-MOSFET (HEMAGASE)-MOSFET, Kirti Goel, Manoj Saxena, Mridula Gupta, R. S. Gupta, 16th Asia Pacific Microwave Conference (APMC-2005), Suzhou, China, December 4-7, 2005, pp. 848-851.
  11. Three Region Hetero-Material Gate Oxide Stack (TMGOS) Epi-MOSFET: A New Device Structure for Reduced Short Channel Effects, R. S. Gupta, Kirti Goel, Manoj Saxena and Mridula Gupta, International Semiconductor Device Research Symposium (ISDRS), Bethesda, Bethesda, Maryland, USA, December 7-9, 2005, pp 72-73.
  12. Comparison of Three Region Multiple Gate Nanoscale Structures for Reduced Short Channel Effects and High Device Reliability, Kirti Goel, Manoj Saxena and Mridula Gupta and R. S. Gupta, Workshop on Compact Modeling (WCM 06), Boston, Massachusetts, U.S.A., NSTI-Nanotech, pp. 816-819, May 9-11, 2006.
  13. Gate Oxide Engineered Dual Material Gate Insulated Shallow Extension (GOXDMG-ISE) MOSFET: A New Vent to Wireless Communication, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, 3rd International Conference on Computers and Devices for Communication (CODEC-2006), Institute of Radio physics and Electronics, Calcutta, pp. 324-327, December 18-20, 2006
  14. Exploration of the Effect of Negative Junction Depth on the Electrical Characteristics of Concave DMG MOSFET in Sub-50-Nanometer Regime, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, 3rd International Conference on Computers and Devices for Communication (CODEC-2006), Institute of Radio physics and Electronics, Calcutta, pp. 317-319, December 18-20, 2006
  15. Dual Material Gate (DMG) SOI-MOSFET with Dielectric Pockets: Innovative Sub-50 nm design for improved switching performance, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R.S. Gupta, Indo-Australian Symposium on Multifunctional Nanomaterials, Nanostructures and Applications (MNNA 2007) December 19 –21, 2007, Department of Physics & Astrophysics, University of Delhi, Delhi, pp. 109
  16. Two-Dimensional Analytical Modeling and Simulation of Rectangular Gate Recessed Channel (RG-RC) Nanoscale MOSFET in Sub-50nm Regime, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, Indo-Australian Symposium on Multifunctional Nanomaterials, Nanostructures and Applications (MNNA 2007) December 19 –21, 2007, Department of Physics & Astrophysics, University of Delhi, Delhi, pp. 110.
  17. A TCAD study of sub-100 nm advance gate electrode workfunction engineered SON-MOSFET, R.S. Gupta, Manoj Saxena and Poonam Kasturi, 11th International Symposium on Microwave and Optical Technology (ISMOT-2007) , Villa Mondragone, Monte Porzio Catone, Italy on 17-21 December 2007, pp. 267-270
  18. Scrutinize the Gate Misalignment Effects in Graded Channel DG FD SOI n-MOSFET, Rupendra Kumar Sharma, Manoj Saxena, Mridula Gupta and R.S. Gupta, 11th International Symposium on Microwave and Optical Technology (ISMOT-2007), Villa Mondragone, Monte Porzio Catone, Italy on 17-21 December 2007, pp, 821-824
  19. Electrical Characterization of Insulated Shallow Extension (ISE) MOSFET: A Punchthrough Stopper, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R.S. Gupta, 11th International Symposium on Microwave and Optical Technology (ISMOT-2007), Villa Mondragone, Monte Porzio Catone, Italy on 17-21 December 2007, pp. 813-816
  20. Pre-Distortion Linearity Enhancement for Sub-50nm Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, 11th International Symposium on Microwave and Optical Technology (ISMOT-2007), Villa Mondragone, Monte Porzio Catone, Italy on 17-21 December 2007, pp.797-800
  21. Linearity assessment in DMG ISEGaS MOSFET for RFIC Design Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R.S. Gupta, Nineteenth Asia Pacific Microwave Conference (APMC-2007), December 11-14, 2007, Bangkok, Thailand, pp.2495-2498
  22. On-State and Switching Performance Investigation of Sub-50nm L-DUMGAC MOSFET Design for High-Speed Logic Applications, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, International Semiconductor Device Research Symposium (ISDRS), University of Maryland, USA, December 12-14, 2007, pp.1892-1893
  23. A 2-D Analytical Subthreshold Model for Gate Misalignment Effects on Graded Channel DG FD SOI n-MOSFET, Rupendra Kumar Sharma, Manoj Saxena, Mridula Gupta and R. S. Gupta, Fourteenth International Workshop on the Physics of Semiconductor Devices (IWPSD-2007) December 16-20, 2007, Mumbai, India, pp. 183-186
  24. RF-Distortion in Sub-100nm L-DUMGAC MOSFET, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Fourteenth International Workshop on the Physics of Semiconductor Devices (IWPSD-2007). December 16-20, 2007, Mumbai, India, pp.168-170
  25. Two-Dimensional Analytical Threshold Voltage Model for Nanoscale SG-Concave MOSFET in Sub-50nm Regime, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, Fourteenth International Workshop on the Physics of Semiconductor Devices (IWPSD-2007), December 16-20, 2007, Mumbai, India, pp. 221-224
  26. Nanoscale Insulated Shallow Extension MOSFET with Dual Material Gate for High Performance Analog Operations , Ravneet Kaur, Rishu Chaujar, Manoj Saxena, and R. S. Gupta, Fourteenth International Workshop on the Physics of Semiconductor Devices (IWPSD-2007) December 16-20, 2007, Mumbai, India, pp. 171-173
  27. Performance Consideration of a Novel Architecture: ISEGaS deca-nanometer MOSFET, Ravneet Kaur, Rishu Chaujar, Manoj Saxena, and R. S. Gupta, Fourteenth International Workshop on the Physics of Semiconductor Devices (IWPSD-2007) December 16-20, 2007, Mumbai, India, pp.123-126
  28. TCAD investigation of a Novel MOSFET architecure of DMG ISE SON MOSFETs for ULSI era, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R.S. Gupta, Mini-Colloquia on Compact Modeling of advance MOSFET structures and mixed mode applications on January 5-6, 2008 at University of Delhi South Campus, New Delhi, India sponsored by the IEEE Electron Device Society under its Distinguished Lecturer Program, pp. 18-19
  29. Analytical analysis of subthreshold performance of sub-100 nm advanced MOSFET structures – An iterative approach, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R.S. Gupta, Mini-Colloquia on Compact Modeling of advance MOSFET structures and mixed mode applications on January 5-6, 2008 at University of Delhi South Campus, New Delhi, India sponsored by the IEEE Electron Device Society under its Distinguished Lecturer Program, pp. 20-21
  30. Modeling and 2-D simulation of Nanoscale SON MOSFET, Poonam Kasturi, Manoj Saxena, Mridula Gupta and R.S. Gupta, Mini-Colloquia on Compact Modeling of advance MOSFET structures and mixed mode applications on January 5-6, 2008 at University of Delhi South Campus, New Delhi, India sponsored by the IEEE Electron Device Society under its Distinguished Lecturer Program, pp. 22-24
  31. Performance advantage of air as buried dielectric in sub-100 nm silicon-on-nothing (SON) MOSFET with gate stack architecture, Poonam Kasturi, Manoj Saxena, Mridula Gupta and R.S. Gupta, Mini-Colloquia on Compact Modeling of advance MOSFET structures and mixed mode applications on January 5-6, 2008 at University of Delhi South Campus, New Delhi, India sponsored by the IEEE Electron Device Society under its Distinguished Lecturer Program, pp. 25-26
  32. Sub-threshold drain current performance assessment of MLGEWE-RC MOSFET for CMOS technology, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, Mini-Colloquia on Compact Modeling of advance MOSFET structures and mixed mode applications on January 5-6, 2008 at University of Delhi South Campus, New Delhi, India sponsored by the IEEE Electron Device Society under its Distinguished Lecturer Program, pp. 27-28
  33. RF performance assessment of L-DUMGAC MOSFET for furure CMOS technology in gigahertz regime, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, Mini-Colloquia on Compact Modeling of advance MOSFET structures and mixed mode applications on January 5-6, 2008 at University of Delhi South Campus, New Delhi, India sponsored by the IEEE Electron Device Society under its Distinguished Lecturer Program, pp. 29-30
  34. An Iterative Approach to Characterize Various Advanced Non-Uniformly Doped Channel Profile, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, 2008 NSTI Nanotechnology Conference and Trade Show, June 1-5, 2008, Boston, Massachusetts, U.S.A. Nanotech 2008 Vol. 3, pp. 814-817
  35. Pre-Distortion Assessment of Workfunction Engineered Multilayer Dielectric Design of DMG ISE SON MOSFET, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, 2008 NSTI Nanotechnology Conference and Trade Show, June 1-5, 2008, Boston, Massachusetts, U.S.A. Nanotech 2008 Vol. 3, pp. 605-606
  36. Assessment of L-DUMGAC MOSFET for High Performance RF Applications with Intrinsic Delay and Stability as Design Tools, R. Chaujar, R. Kaur, M. Saxena, M. Gupta and R. S. Gupta, 2008 NSTI Nanotechnology Conference and Trade Show, June 1-5, 2008, Boston, Massachusetts, U.S.A. Nanotech 2008 Vol. 3, pp. 586-589
  37. Compact Analytical Threshold Voltage Model for Nanoscale Multi-Layered-Gate Electrode Workfunction Engineered Recessed Channel, R. Chaujar, R. Kaur, M. Saxena, M. Gupta and R. S. Gupta, 2008 NSTI Nanotechnology Conference and Trade Show, June 1-5, 2008, Boston, Massachusetts, U.S.A. Nanotech 2008 Vol. 3, pp. 873-876
  38. Nanoscale Analytical Modeling and TCAD Simulations of a Novel Gate Dielectric Stack SDPI MOSFET, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R.S. Gupta, 2nd IEEE International Nanoelectronics Conference (INEC) Pudong, Shanghai in conjunction with the Shanghai Nanophotonics and Electronics Forum from 24-27 March 2008, pp 964-969
  39. TCAD Investigation of Hot Carrier Reliability Issues Associated with GEWE-RC MOSFET, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, 2nd IEEE International Nanoelectronics Conference (INEC) Pudong, Shanghai in conjunction with the Shanghai Nanophotonics and Electronics Forum from 24-27 March 2008, pp. 1434-1437
  40. Impact of Gate Stack Configuration onto the RF/analog Performance of ISE MOSFET., Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, International Conference of Recent Advances in Microwave Theory and Applications, Microwave-2008 conference, Nov. 21 – 24, 2008 at Jaipur, pp. 686-688.
  41. GEWE-RC MOSFET: A solution to CMOS technology for RFIC design based on the concept of intercept point., Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, International Conference of Recent Advances in Microwave Theory and Applications, Microwave-2008 conference, Nov. 21 – 24, 2008 at Jaipur, pp. 661-663.
  42. Impact of Multi-Layered Gate Design on Hot Carrier Reliability of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET, R. Chaujar, R. Kaur, M. Saxena, M. Gupta and R. S. Gupta, XXIX General Assembly of the International Union of Radio Science (Union Radio Scientifique Internationale-URSI), Chicago, Illinois, USA on August 07-16, 2008.
  43. GEWE-RC MOSFET: High Performance RF Solution to CMOS Technology, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, Asia Pacific Microwave Conference (APMC)-2008, December 16-19, 2008 in Hong Kong Convention and Exhibition Center, Hong Kong, China, art. no. 4958185
  44. TCAD Performance Investigation of a Novel MOSFET Architecture of Dual Material Gate Insulated Shallow Extension Silicon on Nothing MOSFET for the ULSI-Era, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R.S. Gupta, Asia Pacific Microwave Conference (APMC)-2008, December 16-19, 2008 in Hong Kong Convention and Exhibition Center, Hong Kong, China, art. no. 4958643
  45. Analytical Drain Current Evaluation Technique for Various Non-Uniformly Doped MOS Device Architectures, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, International Symposium on Microwave and Optical Technology (ISMOT) – 2009, December 16-19,2009 in Hotel Ashok, New Delhi, India
  46. Evaluation of Multi-Layered Gate Design on GEWE-RC MOSFET for Wireless Applications in terms of Linearity-Distortion Issues, Rishu Chaujar, Manoj Saxena, Mridula Gupta and R.S. Gupta, International Symposium on Microwave and Optical Technology (ISMOT)-2009, December 16-19,2009 in Hotel Ashok, New Delhi, India
  47. A Unified Two Dimensional Analytical Model of optically Controlled Silicon On Insulator MESFET ( OPSOI ) for advanced channel materials, Rajni Gautam, Manoj Saxena, R.S. Gupta and Mridula Gupta, The International Conference on Fiber Optics and Photonics – PHOTONICS, December 11-15,2010, IIT Guwahati
  48. A 2-D Subthreshold Analytical model for Short Channel Effects in Nanowire MOSFETs (Si, Ge), Gaurav Mahajan, Rakhi Narang, Manoj Saxena, V.K. Chaubey, Nirma University International Conference on Engineering (NUiCONE) 2010, December 09-11, 2010, Nirma University, Ahmedabad
  49. Fabrication and Time degradation study of mercuric iodide (Red) single crystal X-Ray detector, Kulvinder Singh and Manoj Saxena, International Symposium on Semiconductor Materials and Devices (ISSMD), M. S. University Vadodara, Gujarat, January 28-30, 2011
  50. Simulation Study of Stack Gate Insulated Shallow Extension Silicon On Nothing ISE-SON MOSFET for RFICs design, Vandana Kumari, Manoj Saxena, R. S. Gupta and Mridula Gupta, 2011 IEEE Students' Technology Symposium at IIT Kharagpur during 14-16 January 2011, pp. 286-291.
  51. Modeling and Simulation of multi layer gate dielectric Double Gate Tunnel Field-Effect Transistor (DG-TFET), Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, 2011 IEEE Students' Technology Symposium at IIT Kharagpur during 14-16 January 2011.
  52. Analysis and Simulation of Si/GaAs/GaN MESFET to study the impact of Localised charges on device performance, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, 2011 IEEE Students' Technology Symposium at IIT Kharagpur during 14-16 January 2011, pp. 259-264
  53. Mixedmode Circuit Simulation of Silicon and Germanium Nanowire MOSFETs - A Comparative Study,Gaurav Mahahan, Rakhi Narang, Manoj Saxena and V. K. Chaubey, 2011 IEEE Students' Technology Symposium at IIT Kharagpur during 14-16 January 2011, pp. 292-296.
  54. Nanoscale Double Gate Silicon On Nothing (DGSON) MOSFET: Promising Device Design for Wide Range of Operating Temperatures, Vandana Kumari, Manoj Saxena, Mridula Gupta and R. S. Gupta, International Conference on Latest Trends in Nanoscience and Nanotechnology (ICNSNT), 28th -29th March 2011, Karnataka, India
  55. Impact of a low bandgap material on the Linearity of a DG-TFET: A Comparative Study, Rakhi Narang, Manoj Saxena, Mridula Gupta and R. S. Gupta, International Conference on Latest Trends in Nanoscience and Nanotechnology (ICNSNT), 28th -29th March 2011, Karnataka, India
  56. Study of Performance Degradation of the Nanoscale Cylindrical Surrounding Gate MOSFET due to Hot Carrier Induced Localized Charges, Rajni Gautam, Manoj Saxena, Mridula Gupta and R. S. Gupta, International Conference on Latest Trends in Nanoscience and Nanotechnology (ICNSNT), 28th -29th March 2011, Karnataka, India
  57. Immunity Against Temperature Variability and Bias Point Invariability in Double Gate Tunnel Field Effect Transistor, Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, International Conference on Materials for Advance Technologies, (ICMAT 2011), June 26, 2011 – July 01, 2011, Singapore
  58. SiGe Metal Semiconductor Field Effect Transistor (MESFET) Photodectetor Having Tailorable Photoresponse Using Bandgap Engineering, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, International Conference on Materials for Advance Technologies, (ICMAT 2011), June 26, 2011 – July 01, 2011, Singapore
  59. Simulation Study of Insulated Shallow Extension Silicon On Nothing (ISESON) MOSFET for High Temperature Applications, Vandana Kumari, Manoj Saxena, R. S. Gupta and Mridula Gupta, International Conference on Materials for Advance Technologies, (ICMAT 2011), June 26, 2011 – July 01, 2011, Singapore
  60. High Sensitivity Photodetector Using Si/Ge/GaAs Metal Semiconductor Field Effect Transistor (MESFET), Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, OPTICS 2011, May 23-25, 2011, Calicut, Kerala, India
  61. Impact of Localized Charges on RF and Microwave Performance of Nanoscale Cylindrical Surrounding Gate MOSFET, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, 13thInternational Symposium on Microwave and Optical Technology, ISMOT 2011, Prague, Czech Republic, EU, June 20-23, 2011
  62. RF Performance Analysis of Double Gate Tunneling Field Effect Transistor (DG-TFET), Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, 13th International Symposium on Microwave and Optical Technology, ISMOT 2011, Prague, Czech Republic, EU, June 20-23, 2011
  63. Comparative Study of Dielectric Pocket (DP) MOSFET Incorporating Buried Oxide Layer (BOX) with DP MOSFET for RF Applications, Vandana Kumai, Manoj Saxena, R. S. Gupta and Mridula Gupta,13th International Symposium on Microwave and Optical Technology, ISMOT 2011, Prague, Czech Republic, EU, June 20-23, 2011
  64. Effect of Temperature and Gate Stack on the Linearity and Analog Performance of Double Gate Tunnel FET, Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, The Second International Workshop on VLSI (VLSI 2011) in conjunction with (NECOM-2011), Venue: The Park Hotels, July 15 ~ 17, 2011, Chennai, India.
  65. Channel Material Engineered Nanoscale Cylindrical Surrounding Gate MOSFET With Interface Fixed Charges, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, The Second International Workshop on VLSI (VLSI 2011) in conjunction with (NECOM-2011), Venue: The Park Hotels, July 15 ~ 17, 2011, Chennai, India.
  66. Modeling and Simulation of Dielectric Pocket Double Gate (DP-DG) MOSFET for Low Voltage Low Power Analog Applications, Vandana Kumai, Manoj Saxena, R. S. Gupta and Mridula Gupta, 2011 International Semiconductor Device Research Symposium, December 07-09, 2011, University of Maryland, USA
  67. Analytical Model of a Tunnel FET Based Biosensor for Label Free Detection, Rakhi Narang, K V Sasidhar Reddy, Manoj Saxena, R. S. Gupta and Mridula Gupta, 2011 International Semiconductor Device Research Symposium, December 07-09, 2011, University of Maryland, USA
  68. Investigation of RF/Microwave Performance Degradation for Cylindrical Nanowire MOSFET Due to Interface (Localised) Charges, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, 2011 International Semiconductor Device Research Symposium, December 07-09, 2011, University of Maryland, USA
  69. Drain Current Model of Nanoscale Dual Material Gate (DMG) MOSFET including interfacial hot-carrier-induced degradation effect", Mini, Vandana Kumai, Manoj Saxena, R. S. Gupta and Mridula Gupta, Accepted for Publication in International Conference on Microwaves, Antenna, Propagation and Remote Sensing, ICMARS-2011, Jaipur, India
  70. An Analytical Modeling Approach for a Gate All Around (GAA) Tunnel Field Effect Transistor (TFET), Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, XVI International Workshop on the Physics of Semiconductor Devices, IWPSD 2011, December 19-22, 2011, IIT Kanpur
  71. Digital Circuit Analysis of Insulated Shallow Extension Silicon On Void (ISESOV) FET for Low Voltage Applications, Vandana Kumai, Manoj Saxena, R. S. Gupta and Mridula Gupta, XVI International Workshop on the Physics of Semiconductor Devices, IWPSD 2011, December 19-22, 2011, IIT Kanpur
  72. Influence of Localised charges on the temperature sensitivity of Si nanowire MOSFET, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, XVI International Workshop on the Physics of Semiconductor Devices, IWPSD 2011, December 19-22, 2011, IIT Kanpur
  73. Stability Study on Ceramic Mercuric Iodide (Red) X-Ray Sensor, Kulvinder Singh and Manoj Saxena, XVI International Workshop on the Physics of Semiconductor Devices, IWPSD 2011, December 19-22, 2011, IIT Kanpur
  74. Temperature Dependent RF/microwave Characteristics of Nanowire Surrounding Gate MOSFET with Localised Charges, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, International Conference on Nanoscience and Technology (ICONSAT – 2012), January 20 to 23, 2012 at Hyderabad, India.
  75. Nano-scale Empty Space in Double Gate (ESDG) MOSFET for High Performance Digital Applications: A Theoretical Study, Vandana Kumari, Manoj Saxena, R. S. Gupta and Mridula Gupta, International Conference on Nanoscience and Technology (ICONSAT – 2012), January 20 to 23, 2012 at Hyderabad, India.
  76. Dynamic Performance Comparison of p-i-n and p-n-p-n Tunnel Field Effect Transistor and Impact of Gate Drain underlap , Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, International Conference on Nanoscience and Technology (ICONSAT – 2012), January 20 to 23, 2012 at Hyderabad, India.
  77. Asymmetric Gate Oxide Tunnel Field Effect Transistor for Improved Performance , Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, International Conference On Devices Circuits and Systemes (ICDCS’12) to be held during March 15 - 16, 2012, Karunya Institute of Technology & Sciences, Coimbatore, India
  78. Laterally Asymmeterc Channel Insulated Shallow Extension (LAC-ISE-SON) MOSFET for improved reliability and digital circuit simulation, Vandana Kumari, Manoj Saxena, R. S. Gupta and Mridula Gupta, International Conference On Devices Circuits and Systemes (ICDCS’12) to be held during March 15 - 16, 2012, Karunya Institute of Technology & Sciences, Coimbatore, India
  79. Impact of the localized Charges in the iNterficial Layer of the Schottky Contact in SOI MESFET, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, International Conference On Devices Circuits and Systemes (ICDCS’12) to be held during March 15 - 16, 2012, Karunya Institute of Technology & Sciences, Coimbatore, India
  80. Analytical Drain Current Model for Damaged Gate All Around (GAA) MOSFET Including Quantum and Velocity Overshoot Effects, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, NSTI-Nanotech 2012 Conference and Expo, June 18-21, 2012, Santa Clara, USA, Vol. 2, pp.716-719, 2012
  81. Physics based Analytical Model for a Pocket Doped p-n-p-n Tunnel Field Effect Transistor, Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, NSTI-Nanotech 2012 Conference and Expo, June 18-21, 2012, Santa Clara, USA, Vol. 2, pp.776-779, 2012
  82. Impact of temperature variations on the device and circuit performance of Tunnel FET - A Simulation Study, Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, NANOCON 2012 – Second International Conference on Nanotechnology - Innovative Materials, Processes, Products and Applications, held during October 18-19 2012, at Bharati Vidyapeeth University, Pune, India, pp.99
  83. Comparative Study of Silicon On Nothing and III-V On Nothing Architecture for High Speed and Low Power Analog and RF/Digital Applications, Vandana Kumari, Manoj Saxena, R. S. Gupta and Mridula Gupta, NANOCON 2012 – Second International Conference on Nanotechnology - Innovative Materials, Processes, Products and Applications to be held during October 18-19 2012, at Bharati Vidyapeeth University, Pune, India, pp.105
  84. Gate All Around MOSFET with Catalytic Metal Gate for Gas Sensinga Applications, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, NANOCON 2012 – Second International Conference on Nanotechnology - Innovative Materials, Processes, Products and Applications held during October 18-19 2012, at Bharati Vidyapeeth University, Pune, India, pp.106
  85. Analytical Model for a Dielectric Modulated Double Gate FET (DM-DG-FET) Biosensor, Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, International Conference on Emerging Electronics, Jointly organized by IIT Bombay & IISc Bangalore held during December 15-17, 2012
  86. Temperature Dependent Model for Dielectric Pocket Double Gate (DPDG) MOSFET: A Novel Device Architecture, Vandana Kumari, Manoj Saxena, R. S. Gupta and Mridula Gupta, International Conference on Emerging Electronics, Jointly organized by IIT Bombay & IISc Bangalore held during December 15-17, 2012
  87. Surface Potential based analytical model for Hetero-Dielectric p-n-i-n Double GATE Tunnel FET, Upasana, Rakhi Narang, Manoj Saxena and Mridula Gupta, 17th International Workshop on The Physics of Semiconductor Devices, December 10-13, 2013 organized at Amity University, Noida, India
  88. Ambipolar behaviour of Tunnel Field Effect Transistir (TFET) as an advantage for Biosensiing Applications, Ajay, Rakhi Narang, Manoj Saxena and Mridula Gupta, 17th International Workshop on The Physics of Semiconductor Devices, December 10-13, 2013 organized at Amity University, Noida, India
  89. Simulation Study for Dual Material Gate Hetero- Dielectric TFET: Static Performance Analysis for Analog Applications, Upasana, Rakhi Narang, Manoj Saxena and Mridula Gupta, INDICON 2013, December 13-15, 2013, Victor Menezes Convention Centre (VMCC), IIT Bombay, Mumbai
  90. Investigation of Dielectric-Modulated Double-Gate Junctionless MOSFET For Detection of Biomolecules, Ajay, Rakhi Narang, Manoj Saxena and Mridula Gupta, INDICON 2013, December 13-15, 2013, Victor Menezes Convention Centre (VMCC), IIT Bombay, Mumbai
  91. Hot Carrier Reliability and Linearity Performance Investigation of Nanoscale RingFET for RFIC Design, Sachin Kumar, Vandana Kumari, Manoj Saxena, Mridula Gupta, 9th International Conference on Microwaves, Antenna Propagation and Remote Sensing (ICMARS), held in Jodhpur, Rajasthan, India during 11th – 14th December 2013. (Best Student Paper Award)
  92. Switching Performance analyses of Gate Material and Gate Dielectric Engineered TFET Architectures and Impact of Interface Oxide Charges, Upasana, Rakhi Narang, Manoj Saxena and Mridula Gupta, Accepted in International Conference on Devices, Circuits and Systems – ICDCS 2014. ICDCS 2014 will be held during Mar 6-8, 2014 in Karunya University, Coimbatore, Tamil Nadu, India.
  93. Analytical Modeling of a Split-Gate Dielectric Modulated Metal-Oxide-Semiconductor Field-Effect Transistor for Application as a Biosensor, Ajay, Rakhi Narang, Manoj Saxena and Mridula Gupta, Accepted in International Conference on Devices, Circuits and Systems – ICDCS 2014. ICDCS 2014 will be held during Mar 6-8, 2014 in Karunya University, Coimbatore, Tamil Nadu, India.
  94. TCAD Assesment of Dual Material Gate Nanoscale RingFET (DMG-RingFET) for Analog and Digital Applications, Sachin Kumar, Vandana Kumari, Manoj Saxena, Mridula Gupta, Accepted in International Conference on Devices, Circuits and Systems – ICDCS 2014. ICDCS 2014 will be held during Mar 6-8, 2014 in Karunya University, Coimbatore, Tamil Nadu, India.
  95. Investigate The Bio-sensing Application of Junction less (JL) Double Gate (DG) Tunnel Field Effect Transistor (TFET), Ajay, Rakhi Narang, Manoj Saxena and Mridula Gupta, Accepted in The 6th edition of the Nano Mission (DST), Govt. of India sponsored biennial event -International Conference on Nanoscience and Technology (ICONSAT-2014) will be held during March 3-5, 2014 at Chandigarh, India.
  96. Performance Investigation of Double Gate – RingFET (DG-RingFET) for Analog and Digital Circuit Design, Sachin Kumar, Vandana Kumari, Manoj Saxena, Mridula Gupta, Accepted in The 6th edition of the Nano Mission (DST), Govt. of India sponsored biennial event -International Conference on Nanoscience and Technology (ICONSAT-2014) will be held during March 3-5, 2014 at Chandigarh, India.
  97. The Biosensing Application Of p-type and n-type Dielectric Modulated (DM) Double Gate (DG) Junctionless MOSFETs For Label Free Electrical Detection of Biomolecules, Ajay, Rakhi Narang, Manoj Saxena and Mridula Gupta, Accepted inBiosensor 2014, World Congress on Biosensors be held during May 27-30, 2014 in Melbourne, Australia
  98. Proposal for Junction less Tunnel Field Effect Transistor (JL TFET) as ultra-sensitive for label free Biomolecule Detection, Ajay, Rakhi Narang, Manoj Saxena and Mridula Gupta, Accepted in the 2nd Radio and Antenna Days of the Indian Ocean (RADIO) will be held in Mauritius from 7th to 10th April 2014.
PAPERS IN NATIONAL CONFERENCE PROCEEDINGS
  1. Two-Dimensional Analytical Modeling and Simulation of DMG-EPI MOSFET, Kirti Goel, Manoj Saxena, Mridula Gupta and R. S. Gupta, National conference on VLSI Design & Technology, April 12-13, 2004, Bharati Vidyapeeth’s College of Engineering, Paschim Vihar, New Delhi, India.
  2. Two-Dimensional Analytical Modeling and Simulation of a novel structure Triple-Material Gate Stack (TRIMGAS) MOSFET, R. S. Gupta, Kirti Goel, Manoj Saxena and Mridula Gupta, ELECTRO-2005, Emerging Trends in Electronics, BHU, Varanasi, February 3-5, p.134-137, 2005.
  3. Two-Dimensional Analytical Modeling and Simulation of Multiple Material Gate Oxide Stacked MOSFET, R. S. Gupta, Kirti Goel, Manoj Saxena and Mridula Gupta, National Conference on Integrated Broad Band Digital Systems and Networks, NIEC, Delhi, March 18-19, 2005
  4. RF Performance Investigation of Gate Stacked Insulated Shallow Extension (ISE) MOSFET and Bulk: A Comparative Study, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, Proceeding of Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2006), pp 254-258
  5. Design and FPGA realization of Direct Sequence-Spread Spectrum (DS-SS) BPSK Modulator using a Five Stage Gold Code Generator, Rishu Chaujar, Ravneet Kaur, Manoj Saxena and R. S. Gupta, Proceeding of Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2006), pp 213-216.
  6. Scrambled Sequence FPGA based Direct Sequence Spread Spectrum BPSK Modulator: 10 Stage Analysis, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, National Conference on Recent Trends in Electronics and Information Technology, (RTEIT 2006), pp 334-337, 28-29 July 2006, Maharashtra, India.
  7. Exploring the Effect of Negative Junction Depth on Electrical Behaviour of Sub-50-Nanometer Concave DMG MOSFET: A Simulation Study, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, National Conference on Recent Advancement in Microwave Technique and Applications (Microwave-2006), pp. 123-125, 6-8 October 2006, Jaipur, India.
  8. Lateral Channel Engineered Structure- Insulated Shallow Extension (ISE) MOSFET: DC and RF Performance Investigation, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, National Conference on Recent Advancement in Microwave Technique and Applications (Microwave-2006), pp. 119-122, 6-8 October 2006, Jaipur, India.
  9. Effect of transport property on the performance of insulated shallow extension gate stack (ISEGaS) MOSFET, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, Indian microelectronics Society Conference 2007 Theme: Trends in VLSI and Embedded System, pp. 52-57, August 17-18, 2007, Punjab Engineering College, Chandigarh, India
  10. New Concave MOSFET with Transverse Dual Material Gate (T-DMG) in Sub-50nm Regime: A Simulation Study, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Indian microelectronics Society Conference 2007 Theme: Trends in VLSI and Embedded System, pp. 33-37, August 17-18, 2007, Punjab Engineering College, Chandigarh, India (Best Student Paper Award)
  11. A 2-D Analytical Model for Gate Misalignment Effects on Graded Channel DG FD SOI n-MOSFET, Rupendra Kumar Sharma, Manoj Saxena, Mridula Gupta and R. S. Gupta, Indian microelectronics Society Conference 2007 Theme: Trends in VLSI and Embedded System, August 17-18, 2007, Punjab Engineering College, Chandigarh, India
  12. Development Board-Level Experimentation and Simulation of FPGA based DEBPSK DSSS Modulator: Implementation of 10-Chip Gold Code Sequence Generator, Rishu Chaujar, Ravneet Kaur, Manoj Saxena and R. S. Gupta, Second National Conference on Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2008) September 26-28, 2008 in New Delhi, India, pp. 255-261.
  13. Simulation of a Novel ISE MOSFET with Gate Stack Configuration, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, Second National Conference on Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2008) September 26-28, 2008 in New Delhi, India, pp. 291-296.
  14. Solution to CMOS technology for high performance analog applications: GEWE-RC MOSFET , Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta, R. S. Gupta, 2nd National Workshop on Advanced Optoelectronic Materials and Devices, AOMD 2008, art. no. 5075707, pp. 201-205.
  15. Effect of temperature variation on various parameters in Insulated Shallow Extension Silicon On Nothing(ISE-SON)MOSFET:A simulation study, Vandana Kumari, Manoj Saxena, R. S. Gupta and Mridula Gupta, National Conference and Workshop on Recent Advances in Modern Communication Systems and Nanotechnology (NCMCN – 2011) during January, 06-08, 2011
  16. Performance Comparison of Silicon and SiGe based Double Gate Tunneling Field Effect Transistor with gate stack architecture, Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, National Conference and Workshop on Recent Advances in Modern Communication Systems and Nanotechnology (NCMCN – 2011) during January, 06-08, 2011
  17. Impact of Localised Charges on the performance of the Si Nanowire Surrounding Gate MOSFET, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, National Conference and Workshop on Recent Advances in Modern Communication Systems and Nanotechnology (NCMCN – 2011) during January, 06-08, 2011
  18. Investigation of Linearity Performance of a Double Gate Band to Band Tunnel Field Effect Transistor, Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, 15th VLSI Design and Test Symposium, July 7-9, 2011, Wipro Technologies, Pune, India
  19. Analog Performance of Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET: Simulation study, Vandana Kumari, Manoj Saxena, R. S. Gupta and Mridula Gupta, 15th VLSI Design and Test Symposium, July 7-9, 2011, Wipro Technologies, Pune, India
  20. A Wide Temperature Range ( 50-500K ) Analysis For Nanoscale Surrounding Cylindrical Gate MOSFET With Localised Charges, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, 15th VLSI Design and Test Symposium, July 7-9, 2011, Wipro Technologies, Pune, India
  21. High Performance SiGe Metal Semiconductor Field Effect Transistor (MESFET) Based IR Photodetector, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, XXXVI OSI SYMPOSIUM on Frontiers in Optics and Photonics, 03 - 05 December, 2011, IIT Delhi, New Delhi, India
  22. Modeling and Simulation of Dielectric Pocket Silicon On Nothing (DiPSON) MOSFET, Neha Bhushan and Manoj Saxena, 99th Indian Science Congress held at KIIT University, Bhubneswar during Jan 03 – 07, 2012
  23. Theoretical investigation of back gate bias effect on the electrostatic integrity of Insulated Shallow Extension Silicon on Void (ISESOV) MOSFET, Vandana Kumari, Mridula Gupta, Neha Bhushan, Manoj Saxena and R.S. Gupta, 2012 Annual IEEE India Conference, INDICON 2012 , art. no. 6420706 , pp. 694 – 699, 2012
  24. Impact of Insulating Layers on Single and Double Gate MOSFET for Improved Short Channel Effect and Hot Carrier Reliability , Vandana Kumari, Manoj Saxena, R. S. Gupta and Mridula Gupta, First National Conference on Recent Developments in Electronics (NCRDE 2013), Department of Electronic Science, University of Delhi South Campus, New Delhi during Jan 18-20, 2013
  25. High Performance Low Power 6T RAM Cell Using Gate-All Around (GAA) MOSFET , Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, First National Conference on Recent Developments in Electronics (NCRDE 2013), Department of Electronic Science, University of Delhi South Campus, New Delhi during Jan 18-20, 2013
  26. Performance Investigation of Silicon Nanowire Tunnel FET for Analog and Digital Applications, Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, First National Conference on Recent Developments in Electronics (NCRDE 2013), Department of Electronic Science, University of Delhi South Campus, New Delhi during Jan 18-20, 2013
RESEARCH PROJECTS
  1. • Principal Ivestigator in a University of Delhi Sposnored Project under Innovation Project Scheme etitled Analytical Modeling, Simulation and Verification of Emerging Nanoscale MULTIGATE Device Structures and Study of Government’s Initiatives for Growth of Electronics In India, Project Code – 202 (2013) worth Rs. 5,50,000/- On Going - (November 2013 – Till date)
  2. Co-Project Investigator in a DST Sponsored Project entitled Analytical Modelling and Simulation of Sub-100 nm Advance Tunnel FET architecture for RF/ Microwave and Biosensing Applications, (SR/S3/EECE/0062/2012) worth Rs. 31,14,000. On Going - (September 2012 – Till date)
  3. Co-Project Investigator in a DRDO sponsored Project entitled Analytical Modeling, Simulation and Characterization of Silicon Gate All Around Nanowire MOSFET for ULSI (Ultra Large Scale Integration) Circuit Applications worth Rs. 30,68,000. On Going - (April 2012 – Till date)
  4. Co-Project Investigator in a DRDO sponsored Project entitled Physics Based Modeling and Simulation of Sub-100 nm recessed channel (RC) and insulated shallow extension (ISE) MOSFET with gate electrode work function engineering structures for high performance applications (ERIP/ER/0803693/M/01/1258) worth Rs. 4.70 lakhs. On Going - (October 2010 – July 2012)
  5. Co-Principal Investigator in UGC, Govt. of India sponsored research project entitled Modeling and simulation of Nanoscale Dual Material Gate Insulated Shallow Extension Silicon on Nothing MOSFET for Low voltage low power applications (F. No. 36-258/2008(SR)) worth Rs. 9,22,800. On Going - (May 2009 – April 2012)
  6. Co-Project Investigator in a DRDO sponsored Project entitled Physics Based Modeling Simulation and Electrical Characterization of a Novel Device Architecture: Silicon-On-Nothing MOSFET for Sub-100 nm Device Dimensions (No. ERIP/ER/0303417/M/01) worth Rs. 31.68 Lakhs. Completed - (April-2004-December 2007)
AWARDS AND DISTINCTIONS
  • Received Smt. Shanti Devi Bhargava Memorial Gold medal for being best candidate in the M. Sc Examination in Electronics in 2000
  • Name appeared in the Golden List of IEEE Transactions on Electron Devices Reviewers for year 2005, 2006, 2008, 2009 and 2010.
  • Name listed in the 25th Anniversary edition of Who’s Who in the World.
  • Research work has been highlighted in The Telegraph newspaper, April 14, 2003
  • Reviewer for Book Proposal for Universities Press (India) Pvt. Ltd. Hyderabad. (2009 - )
  • Reviewer for Book Proposal for Cambridge Universities Press (India) Pvt. Ltd. (2013 - )
  • Member-Review Committee - International Conference on Latest Trends in Nanoscience and Nanotechnology (ICNSNT), 28th -29th March 2011, Karnataka, India
  • Member of Task Force constituted by University of Delhi for Four Year Syllabus at Undergraduate Courses
  • Reviewer of IEEE Transactions on Electron Devices
  • Reviewer of Journal of Physics D: Applied Physics, Institute of Physics (IOP))
  • Reviewer of Semiconductor Science Technology, Institute of Physics (IOP))
  • Reviewer of Measurement Science and Technology (IOP)
  • Reviewer of Solid State Electronics, Elsevier Science, UK
  • Reviewer of Superlattices and Microstructures, Elsevier Science, UK
  • Reviewer of International Journal of Numerical Modeling: Electronic Networks, Devices and Fields, Wiley
  • Reviewer of IET Micro and Nano Letters
  • Reviewer of Journal of Electrical and Electronics Engineering Research (JEEER)
  • Reviewer of Journal of Electrical Engineering & Technology
  • Reviewer of MAPAN-Journal of Metrology Society of India
  • Reviewer of International Journal of Science and Technology Education Research
  • Reviewer of Asia Pacific Microwave Conference (APMC)-2008, 16-19, December 2008 in Hong Kong Convention and Exhibition Center, Hong Kong, China
  • Reviewer of International Symposium on Microwave and Optical Technology (ISMOT)-2009,16-19, December 2009 in Hotel Ashok, New Delhi, India
  • Reviewer of The 8th International Conference on Computing, Communications and Control Technologies: CCCT 2010, Jointly with The 16th International Conference on Information Systems Analysis and Synthesis: ISAS 2010, In the Context of The International Multi-Conference on Complexity, Informatics and Cybernetics: IMCIC 2010, April 6th - 9th, 2010 Orlando, Florida USA
  • Reviewer of National Conference on Recent Trends in Exotic materials (NCRTEM 10), Sharda University Greater Noida-201306, U.P., India
  • Reviewer of 7th International Conference on Distributed Computing and Internet Technologies (ICDCIT – 2011), Bhubaneswar during 9 – 12 February 2011.
  • Reviewer of The SPRING 9th International Conference on Computing, Communications and Control Technologies: CCCT 2011 Jointly with The 17th International Conference on Information Systems Analysis and Synthesis: ISAS 2011 In the Context of The 2nd International Multi-Conference on Complexity, Informatics and Cybernetics: IMCIC 2011, March 27th - 30th, 2011 ~ Orlando, Florida USA
  • Reviewer of The 4th International Multi-Conference on Engineering and Technological Innovation: IMETI 2011, July 19th - July 22nd, 2011 – Orlando, Florida, USA, International Symposium on Models and Modeling Methodologies in Science and Engineering: MMMse 2011 in the context of The 15th World Multi-Conference on Systemics, Cybernetics and Informatics: WMSCI 2011, July 19th - July 22nd, 2011 – Orlando, Florida, USA
  • Jury Member of DST INSPIRE JURY: 2nd National Level Exhibition and Project Competition (NLEPC), 2012, Delhi
  • Jury Member of DST INSPIRE JURY: 3rd National Level Exhibition and Project Competition (NLEPC), 2013, Delhi
  • Member of Task Force constituted by University of Delhi for Four Year Syllabus at Undergraduate Courses (2013)
  • Member of Empowered Committee – Information Technology (Foundation Course) constituted by University of Delhi for Four Year Syllabus at Undergraduate Courses (2013)
  • Reviewer of technical papers submitted to 10th International Conference on Distributed Computing and Internet Technologies, 6th - 9th February, 2014, Bhubaneswar, Odisha, India.
ASSOCIATION WITH PROFESSIONAL BODIES
  • Secretary - Institute of Physics (UK)- Delhi Chapter (2013 - )
  • Executive Committee Member – IET(UK) Delhi Network
  • Member – Compact Modeling India SIG
  • Member - MOS Modeling and Parameter Extraction Working Group - MOS-AK/GSA India
  • Member of Editorial Board of International Scholarly Research Network (ISRN) Electronics - http://www.isrn.com/32538140/
  • MInstP - Member – Institute of Physics (IOP), UK in May 2011
  • Expert Member - Directory of researchers working in the country in the area of Nano Science and Technology, Nano Mission, Department of Science and Technology, Govt. of India
  • Associate – Indian Academy of Sciences (IAS), India (2009 - 2012)
  • M. N. A. Sc – Member, National Academy of Sciences India (NASI), Allahabad, India (2009 - ) (at the Age of 31)
  • Senior Member – IEEE, USA (July 2008)
  • MIET - Member – Institution of Engineering and Technology (IET), United Kingdom (UK) (2008-)
  • Secretary – IEEE EDS Delhi Chapter, New Delhi, India (2010 – Till date)
  • Member - International Association of Engineers, Hong Kong (Membership No: 64986)
  • Life Member – Semiconductor Society of India, New Delhi, India
  • Life Member - Indian Science Congress Association (ISCA) (Membership No. L13169)
  • Joint Secretary – Society for VLSI and Microelectronics, New Delhi, India (2008-)
  • Joint Secretary and Treasurer – IEEE EDS Delhi Chapter, New Delhi, India (2009)
  • Member – Electronic Devices Society, USA (2008-)
CONFERENCE/WORKSHOP/SEMINAR/SYMPOSIUM/COLLOQUIA ORGANIZED
  1. 2003 - Member - Organizing Committee National Symposium on recent advances in microwaves and light waves (NSAML’03) University of Delhi South Campus, New Delhi, October 2003.
  2. 2004 - Joint Secretary and Member - Technical Review Committee 16th Asia-Pacific Microwave Conference (APMC’2004), University of Delhi, December 15 - 18, 2004, New Delhi, India
  3. 2005 - Treasurer and Member Organizing Committee Short course on Spice Models for Advanced VLSI Circuit Simulation organized by Department of Electronic Science, University of Delhi South Campus, December 11-12, 2005
  4. 2006 - Secretary and Member-Technical Programme Committee National Conference on Mathematical Techniques: Emerging Paradigms for Electronics and IT Industries (MATEIT-2006) from 22nd March – 25th March 2006, Deen Dayal Upadhyaya College, University of Delhi, Shivaji Marg, New Delhi, India
  5. 2006 - Member - Local organizing committee - India-Japan Workshop (IJW-2006) on ZnO Materials and Devices, December 18-20, 2006 sponsored by DST (New Delhi) - JSPS (Japan) organized by Department of Electronic Science, University of Delhi South Campus
  6. 2008 - Secretary Mini-Colloquia on Compact Modeling of advance MOSFET structures and mixed mode applications on January 5-6, 2008 at University of Delhi South Campus, New Delhi, India sponsored by the IEEE Electron Device Society under its Distinguished Lecturer Program
  7. 2008 - Co-convener and Secretary, National Conference on Mathematical Techniques: Emerging Paradigms for Electronics and IT Industries (MATEIT-2008) from 26th September – 28th September 2008, Deen Dayal Upadhyaya College, University of Delhi, Shivaji Marg, New Delhi, India
  8. 2008 - Coordinator, Two-Days Workshop On Quantum Mechanics: Theory and Application during November 21-22, 2008, Organized by Forum for Interdisciplinary Application in Sciences (FiDAS) Deen Dayal Upadhyaya College, University of Delhi, New Delhi Sponsored by Delhi Chapter of the National Academy of Sciences, India.
  9. 2009 - Co-convener and Secretary, Three days Workshop on Futuristic trends of Quality Control in Information Security Management, Sponsored by CSIR, Govt. of India, October 09-11, 2009 organized by Forum for Interdisciplinary Application in Sciences (FiDAS) Deen Dayal Upadhyaya College, University of Delhi, New Delhi
  10. 2009 - Member-Organizing Committee, National Seminar and Workshop on Integrating Multiple Technologies to Support Teaching and Learning, September 24-26, 2009 organized by Department of Electronics, Maharaja Agarasen College, University of Delhi and sponsored by UGC, Govt. of India
  11. 2009 - Coordinator, First One-Day National Workshop on Einstein & Special Theory of Relativity, Sponsored By Delhi Chapter-National Academy of Sciences, India, November 06, 2009. In all 101 participants participated in the workshop. A brief description of institution wise participation:
  12. 2009 - Coordinator, Second One-Day National Workshop on Einstein & Special Theory of Relativity, Sponsored By Delhi Chapter-National Academy of Sciences, India, November 07, 2009. In all 91 participants participated in the workshop. A brief description of institution wise participation:
  13. 2009 - Coordinator, Two-Day National Workshop on Fiber Optics and Applications, Sponsored By Delhi Chapter-National Academy of Sciences, India, November 28-29, 2009.
  14. 2009 - Secretary, The 18th WIMNACT(Workshop and IEEE EDS Mini-colloquium on NAnometer CMOS Technology)-New Delhi, India - Mini-Colloquia on Compact Modeling and Fabrication techniques of advance MOSFET/ HEMT structures, June 04-05, 2009 at University of Delhi South Campus, New Delhi, India sponsored by the IEEE Electron Device Society under its Distinguished Lecturer Program
  15. 2010 - Co-convener and Secretary, Third National Conference on Mathematical Techniques: Emerging Paradigms for Electronics and IT Industries (MATEIT-2010) held during January 30-31, 2010, Deen Dayal Upadhyaya College, University of Delhi, Shivaji Marg, New Delhi, India, sponsored By University Grants Commission (UGC), Govt. of India
  16. 2010 - Convener, First National Workshop On Recent Trends in Semiconductor Devices and Technology, Jointly Organized By Aryabhatta Science Forum, Deen Dayal Upadhyaya College, University of Delhi And IEEE EDS Delhi Chapter, New Delhi, Supported By Integrated Microsystem, Gurgaon, India, Society for Microelectronics and VLSI, New Delhi, February 12-13, 2010.
  17. 2010 - Convener, Second National Workshop On Recent Trends in Semiconductor Devices and Technology, Jointly Organized By FiDAS, Deen Dayal Upadhyaya College, University of Delhi And IEEE EDS Delhi Chapter, New Delhi, Supported By DRDO, Govt of India and Integrated Microsystem, Gurgaon, India held during September 17-18, 2010
  18. 2010 - Convener, Second National Workshop On Quantum Mechanics: Theory and Application Organized By FiDAS, Deen Dayal Upadhyaya College, University of Delhi, Sponsored By CSIR, Govt of India Supported By IEEE EDS Delhi Chapter, New Delhi and The National Academy of Sciences, India, - Delhi Chapter held during October 22-23, 2010 and October 29-30, 2010.
  19. 2011 - Workshop Coordinator, Three Day Joint Science Academies Lecture Workshop On Frontier in Physics, January 21-23, 2011 jointly Organized by FIDAS, Deen Dayal Upadhyaya College and IEEE EDS Delhi Chapter at SP Jain centre, University of Delhi South Campus, New Delhi.
  20. 2011 - Secretary, First National Workshop On Numerical Methods and Differential Equations in Computational Science (NUMDECS-2011), February 01-05, 2011 Organized by FIDAS, DDU College, Sponsored and Supported by University Grants Commission (UGC), Govt. of India
  21. 2011 - Organizing Committee Member, National Seminar on Recent Advances in Microelectronics Devices, Organized by Department of Electronics and Communication Engineering, Maharaja Agrasen Institute of Technology, Sec-22, Rohini, Delhi-110086 sponsored by Defence Research and Development Organization Ministry of Defence, Government of India.
  22. 2011 - Program Committee Member, The Seventh International Conference on Distributed Computing and Internet Technology, Bhubaneswar, India, 9 – 12 February 2011
  23. 2012 - Technical Program Committee Member, International Conference on Soft Computing for Problem Solving (SoCProS 2011), Roorkee, India, December 20-22, 2011
  24. 2012 - Secretary, Mini-Colloquia on "Compact Modelling Techniques for Nanoscale Devices and Circuit Analysis” Organized by IEEE EDS-Delhi Chapter, New Delhi, India during March 14-15, 2012 held at SP Jain Centre Auditorium, University of Delhi South Campus, Benito Juarez Road, New Delhi, 110021. The Mini-Colloquia was sponsored by the IEEE Electron Devices Society under its Distinguished Lecturer Program
  25. 2012 - Member-Organizing Committee, International MOS-AK/GSA (India) workshop in March 16-17, 2012 in JIIT University, Noida, Uttar Pradesh, India
  26. 2012 - Technical Program Committee Member, Seventh International Conference on “Bio-Inspired Computing: Theories and Application, 2012 (BIC-TA 2012)” ABV-Indian Institute of Information Technology and Management Gwalior during December 14 - 16, 2012.
  27. 2012 - Convener, Science Academies Lecture Workshop On Frontiers in Science & Engineering - Opportunities for Graduates, February 17-18, 2012, SP Jain Centre Auditorium, University of Delhi South Campus, Benito Juarez Road, Dhaula Kuan, New Delhi
  28. 2012 - Convener, Science Academies Lecture Workshop On Joint Academies Lecture Workshop On History, Aspects and Prospects of Electronics in India, October 12-13, 2012, SP Jain Centre Auditorium, University of Delhi South Campus, Benito Juarez Road, Dhaula Kuan, New Delhi.
  29. 2013 - Convener, Third National Workshop On Recent Trends in Semiconductor Devices and Technology, January 19-20, 2013 Jointly organized by Deen Dayal Upadhyaya College, University of Delhi and IEEE EDS Delhi Chapter, New Delhi Sponsored By Defence Research and Development Organization (DRDO), Ministry of Defence, Government of India.
  30. 2013 - Secretary, First National Conference on Recent Developments in Electronics (NCRDE 2013) is being organized by IEEE EDS Delhi Chapter. The conference will be held at Department of Electronic Science, University of Delhi South Campus, New Delhi during Jan 18-20, 2013
  31. 2013 - Convener, Lecture Workshop on Trans-disciplinary Areas of Research and Teaching by Shanti Swaroop Bhatnagar Awardee, February 01-02, 2013 organized by Deen Dayal Upadhyaya College, University of Delhi sponsored by Council of Scientific and Industrial Research (CSIR), New Delhi and supported by IEEE EDS Delhi Chapter
OTHER ACTIVITIES

Research Activities with Undergraduate students
(Summer Research Fellowship Sponsored by Indian Academy of Sciences (IAS), National Academy of Sciences, India (NASI) & Indian National Science Academy (INSA))

  1. Jagriti Mishra, B. Tech, BITS Meshra, ENGS1368),May-July 2010
  2. Gaurav Mahajan, B.E. (Hons.) ,Electrical and Electronics Engineering,Birla Institute of Technology and Science, Pilani (ENGS2982),May-July 2010
  3. Neha Bhushan, KIIT University, Bhubaneswar, (ENGS2269) May-July 2011
  4. K V Sasidhar Reddy, NIT, Warangal, (ENGS4147),May-July 2011
  5. Neel Modi, (ENGS7096), Electronics and Communication Engineering, Sardar Vallabhbhai National Institute of Technology (SVNIT), Surat
  6. Pranav P Nair, (ENGS 5351), B. Tech III Year, Electrical Engineering, IIT Indore, India

 

Papers Published through Summer Research Fellowship Students Sponsored by Indian Academy of Sciences (IAS), National Academy of Sciences, India (NASI) & Indian National Science Academy (INSA))

  1. A 2-D Subthreshold Analytical model for Short Channel Effects in Nanowire MOSFETs (Si, Ge), Gaurav Mahajan, Rakhi Narang, Manoj Saxena, V.K. Chaubey, Nirma University International Conference on Engineering (NUiCONE) 2010, December 09-11, 2010, Nirma University, Ahmedabad
  2. Mixedmode Circuit Simulation of Silicon and Germanium Nanowire MOSFETs - A Comparative Study,Gaurav Mahahan, Rakhi Narangi, Manoj Saxena and V. K. Chaubey, 2011 IEEE Students' Technology Symposium, IIT Kharagpur during 14-16 January 2011.
  3. Modeling and Simulation of Dielectric Pocket Silicon On Nothing (DiPSON) MOSFET, Neha Bhushan and Manoj Saxena, 99th  Indian Science Congress, KIIT University, Bhubneswar during Jan 03 – 07, 2012
  4. Theoretical investigation of back gate bias effect on the electrostatic integrity of Insulated Shallow Extension Silicon on Void (ISESOV) MOSFET, Vandana Kumari, Mridula  Gupta, Neha Bhushan, Manoj Saxena and R.S. Gupta, 2012 Annual IEEE India Conference, INDICON 2012 , art. no. 6420706 , pp. 694 – 699, 2012
  5. A Dielectric Modulated Tunnel FET based Biosensor for Label Free Detection: Analytical Modeling Study and Sensitivity Analysis, Rakhi Narang, K. V. Sasidhar Reddy, Manoj Saxena, Mridula Gupta and R. S. Gupta, IEEE Transactions on Electron Devices, Vol. 59, No. 10, pp. 2809-2817, October 2012

This webpage was last Updated on Jan 27, 2014

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